PCIe Driver Basics — The Bus That Carries Most Modern Hardware
A short explainer of the PCIe bus from a driver-author point of view — capabilities, lanes, generations, and link training.
What the Bus Exposes
PCIe gives every attached device a small block of configuration space — vendor and device identifiers, class codes, and a list of capabilities the device supports. Drivers read this block to decide whether to attach and which features to enable.
Once a driver attaches, it talks to the device through one or more memory-mapped registers and through Dma transfers. The bus also handles power management and reset signals on behalf of the driver.
Lanes and Generations
PCIe links come in widths — one, four, eight, sixteen lanes. Each generation roughly doubles the per-lane bandwidth. A device negotiates with the slot at boot to pick the best width and generation both ends support.
For some devices the link width is critical — a graphics card pinched into a four-lane slot performs noticeably worse than the same card in a sixteen-lane slot. For others, like most network adapters, the link is rarely the bottleneck.
When the Driver Notices Link Issues
Drivers expose link width and generation through their properties. If a device negotiates a lower link than expected, the driver can warn — common causes are a slot that physically supports fewer lanes than it looks, or a Bios setting that splits lanes between slots.
For Nvme drives in particular, link state is worth a check — a fast drive in a slow slot is a common source of unexpected throughput numbers.
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